1. Field of the Invention
The present invention relates to the field of semiconductor manufacturing, and, more particularly, to the formation of an interconnect structure having a contact plug for directly connecting a gate line with a drain/source region of a transistor.
2. Description of the Related Art
Semiconductor devices, such as advanced integrated circuits, typically contain a large number of circuit elements, such as transistors, capacitors, resistors and the like, which are usually formed in a substantially planar configuration on an appropriate substrate having formed thereon a crystalline semiconductor layer. Due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements generally may not be established within the same level on which the circuit elements are manufactured, but require one or more additional “wiring” layers, which are also referred to as metallization layers. These metallization layers generally include metal-containing lines, providing the inner-level electrical connection, and also include a plurality inter-level connections, which are also referred to as “vias,” that are filled with an appropriate metal and provide the electrical connection between two neighboring stacked metallization layers.
To establish the connection of the circuit elements with the metallization layers, an appropriate vertical contact structure is provided that connects to a respective contact region of a circuit element, such as a gate electrode and the drain/source regions of transistors, and to a respective metal line in the first metallization layer. The contact plugs and regions of the contact structure are formed in an interlayer dielectric material that encloses and passivates the circuit elements. In some circuit configurations, a connection of individual areas of a circuit element with other individual areas of the same or other circuit elements, such as a connection from a gate electrode or a polysilicon line to an active semiconductor region, such as a drain/source region, may be established by means of the contact structure on the basis of respective contact regions. One example in this respect is the wiring scheme of certain memory devices in which respective contact trenches, frequently called CAREC contacts, connect the gate electrode or polysilicon lines with a drain/source region.
During the formation of respective contact regions directly connecting individual contact regions of circuit elements, however, a plurality of issues may arise, in particular for highly advanced semiconductor devices having critical feature sizes of 100 nm and even less. With reference to FIGS. 1a-1d, a typical conventional process flow for forming respective contact regions for directly connecting polysilicon lines or gate electrodes with respective active semiconductor regions, i.e., drain/source regions, will be described in more detail in order to more clearly demonstrate the problems involved therein.
FIG. 1a schematically shows a semiconductor device 100, which may represent any appropriate circuit, in which a direct contact region, a so-called CAREC, may be formed to connect adjacent circuit regions. The semiconductor device 100 may comprise a substrate 101, which may represent any appropriate substrate, such as a bulk silicon substrate, a silicon-on-insulator (SOI) substrate and the like. The substrate 101 has formed thereon a substantially crystalline semiconductor layer 102 on and in which respective circuit elements are formed, one of which is indicated as element 120. A trench isolation 103 may be formed within the semiconductor layer 102 to define an active semiconductor region 111, which is to be understood as a doped semiconductor region, in which at least a portion is configured in substantially the same way as a drain or source region of a field effect transistor of the device 100. Consequently, the active region 111 may comprise implanted areas 107, 107e, which may conveniently be referred to as drain/source regions 107 with respective extension regions 107e. Moreover, the device 100 may comprise a polysilicon line 104, which may be formed above the active region 111 and which may be separated therefrom by an insulation layer 105, wherein the polysilicon line 104 may be substantially formed according to design criteria as are also used for the formation of gate electrode structures in the device. On sidewalls of the polysilicon line 104, respective sidewall spacers 106 may be formed which are typically comprised of silicon nitride. Respective metal silicide regions 108 may be formed on top of the polysilicon line 104 and in the drain/source region 107 and a contact etch stop layer 109, typically comprised of silicon nitride, may be formed on the active region 111 and the polysilicon line 104 including the sidewall spacers 106. Finally, an interlayer dielectric material 110 may be formed above the circuit element 120 represented by the polysilicon line 104 and the active region 111 so as to enclose and passivate the circuit element 120.
A typical process flow for forming the semiconductor device 100 as shown in FIG. 1a may comprise the following processes. The insulation layer 105 and the polysilicon line 104 may be formed on the basis of well-established oxidation, deposition, photolithography and etch techniques, wherein lateral dimensions of the polysilicon line 104 may be formed in accordance with device requirements, wherein, in sophisticated devices, the lateral dimension may be approximately 100 nm and even less. Thereafter, the sidewall spacers 106 may be formed by well-established deposition and anisotropic etch techniques, wherein prior to and after the formation of the sidewall spacer 106, which may be comprised of a plurality of spacer elements, appropriate implantation processes may be performed in order to form the source/drain region 107 including the extension region 107e. Next, the metal silicide regions 108 may be formed, for instance, by depositing an appropriate refractory metal and initiating a silicidation process on the basis of an appropriate heat treatment. After the removal of any excess material, the contact etch stop layer 109 may be formed on the basis of well-established plasma enhanced chemical vapor deposition (PECVD) techniques followed by the deposition of the interlayer dielectric material 110, which is typically comprised of silicon dioxide. After any planarization processes, such as chemical mechanical polishing (CMP) and the like, for providing a substantially planar surface of the interlayer dielectric material 110, an appropriate photolithography process may be performed on the basis of a corresponding photolithography mask in order to form a resist mask (not shown) having respective openings corresponding to respective contact openings to be formed above the polysilicon line 104 and the drain/source region 107 to establish a direct electric connection therebetween. Based on a corresponding resist mask, an anisotropic etch process may be performed, which may then be stopped in and on the contact etch stop layer 109 due to the high etch selectivity of the corresponding etch recipe for etching through the silicon dioxide material of the layer 110. Subsequently, a further etch step may be performed to open the contact etch stop layer 109 in order to contact the polysilicon line 104, i.e., the respective metal silicide region 108 formed thereon, and the drain/source region 107, i.e., the corresponding metal silicide region 108 formed therein. During the respective etch process, the sidewall spacers 106 at least at the side of the drain/source region 107 may also be completely removed, since the contact etch stop layer 109 and the spacers 106 are comprised of the same material and a certain degree of over-etch is required to reliably expose the respective metal silicide regions 108. Consequently, during this over-etch time, the etch front may also attack, after having removed the sidewall spacer 106, the extension region 107e so that the etch front may penetrate the extension region 107e to a certain degree thereby possibly creating a short to the remaining active region 111 or at least providing a significant risk of increased leakage currents of the resulting electric connection.
FIG. 1b schematically shows the semiconductor device 100 after the completion of the above-described process sequence. Moreover, the semiconductor device 100 comprises a contact region 112, which may be filled with a conductive material, such as tungsten, wherein, at sidewall portions 112S and bottom portions 112B, a conductive barrier material, such as titanium and the like, may be provided. Since the contact region 112 is connected to the respective metal silicide regions 108 of the polysilicon line 104 and the drain/source region 107, a direct electrical connection between these two device areas is established. Moreover, as previously indicated, the etch process for forming a respective contact opening in the interlayer dielectric material 110 and the contact etch stop layer 109 may have created a recess 113 in the extension region 107e, which may even extend into the active region 111 below the extension region, which may be referred to as a well region, thereby possibly creating a short or at least a current path for increased leakage currents. Subsequently, the contact region 112 may be formed on the basis of well-established recipes, comprising, for instance, the deposition of the barrier layer 114 in accordance with well-established chemical vapor deposition (CVD), physical vapor deposition (PVD) techniques, followed by any appropriate fill technique, such as CVD on the basis of appropriate precursor materials. After removing any excess material of the barrier material and the conductive material comprising the contact region 112, a further passivation layer may be deposited.
As a result, the conventional technique may lead to increased leakage currents or even short circuits between portions 113 of the active region 111 that are inversely doped with respect to the drain/source regions 107 and the extension regions 107e, thereby significantly negatively affecting the performance of the device 100.
FIG. 1c schematically shows the semiconductor device 100 according to a similar configuration as shown in FIG. 1a, in which the circuit element 120 may represent a field effect transistor having substantially the same components as previously described with reference to FIG. 1a. Moreover, a resist mask 115 is formed above the interlayer dielectric material 110, wherein an opening 115A is formed in the resist mask 115 that substantially corresponds to the dimensions of a respective contact opening to be formed in the interlayer dielectric material 110 for providing a direct electric contact from the gate electrode 104 to the respective drain/source regions 107. Moreover, the device 100 is subjected to an anisotropic etch process 116 for etching through the interlayer dielectric material 110, wherein similarly, as is previously described, the etch process 116 may, in a first step, comprise a high etch selectivity with respect to the materials of the layers 110 and the contact etch stop layer 109. After opening the material of the layer 110, a further etch process may be performed to open the contact etch stop layer 109 and reliably remove any material thereof to connect to the respective metal silicide regions 108. During the significant over-etch time of this etch process, sidewalls of the gate electrode 104 are increasingly exposed to the respective etch ambient, which may result in a significant material erosion of the gate electrode 104.
FIG. 1d schematically illustrates the semiconductor device 100 after the completion of the above-described etch process. Consequently, the gate electrode 104 may have suffered severe etch damage, which may result in reduced device reliability and integrity. For example, the mechanical stability of the gate electrode 104 may be significantly reduced, which may lead to an increased defect rate in subsequent manufacturing processes, such as resist removal, cleaning processes prior to the deposition of a barrier material and the subsequent filling in of the conductive contact material. Consequently, the conventional contact technology for providing direct contacts between polysilicon lines and active semiconductor regions may additionally suffer from reduced mechanical integrity and increased defect rate.
In view of the situation described above, there exists a need for an enhanced technique that may enable the formation of contact regions for directly connecting contact regions of circuit elements within the contact structure while avoiding or at least reducing the effects of one or more of the problems identified above.